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q4.4: we add an l2 cache (the earlier cache is the l1 cache), which has a hit time of 20 cycles. we run a program that exhibits an 80% l1 hit rate, and a 95% l2 hit rate (note that the l2 hit rate only counts accesses that miss on the l1 cache). our miss penalty is still the 100 clock cycles needed to access main memory. what is the amat for this cache setup on this program?

Sagot :

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