Consider the following three CPU organizations:
CPU SS: A two-core superscalar microprocessor that provides out-of-order issue capabilities on two function units (FUs). Only a single thread can run on each core at a time.
CPU MT: A fine-grained multithreaded processor that allows instructions from two threads to be run concurrently (i.e., there are two functional units), though only instructions from a single thread can be issued on any cycle.
CPU SMT: An SMT processor that allows instructions from two threads to be run concurrently (i.e., there are two functional units), and instructions from either or both threads can be issued to run on any cycle.
Assume we have two threads X and Y to run on these CPUs that include the following operations:
Thread X
Thread Y
A1 â takes 4 cycles to execute
B1 â takes 2 cycles to execute
A2 â no dependences
B2 â conflicts for a functional unit with B4
A3 â conflicts for a functional unit with A1
B3 â depends on the result of B2
A4 â depends on the result of A1
B4 â no dependences and takes 2 cycles to execute
Assume all instructions take a single cycle to execute unless noted otherwise or they encounter a hazard.
a. Assume that you have one SS CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards?
Cycle
Core 1
Core 2
b. Now assume you have two SS CPUs. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards?
Cycle
Core 1
Core 2
Core 1
Core 2
c. Assume that you have one MT CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards?
Cycle
FU
FU
d. Assume you have one SMT CPU. How many cycles will it take to execute the two threads? How many issue slots are wasted due to hazards?
Cycle
FU
FU