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You are given the following design parameters, fill in the table: All memory addresses are 32-bit long; A 64Kbyte (2^16 byte) cache is added between the processor and the memory. (64Kbytes do not include the amount of space used to store tags and status bits); There are two associativity choices for the cache: direct-mapped and 2-way set associative. There is a 20 percent increase in cache access time and a 40 percent miss rate reduction when moving from a direct-mapped cache to a 2-way set associative cache: There are two cache block size choices of 16bytes and 32bytes. It takes 20 ns to retrieve 1 Gbytes of data from the main memory and 25 ns to retrieve 32 bytes of data. The cache returns the value to the processor after the entire cache block is filled. However, the cache miss rate is reduced by 25 percent when the cache block size doubles; It takes 10ns to access a 64Kbyte direct-mapped cache; The cache nuss rate for a 64Kbyte direct-mapped cache is 10 percent

Sagot :

Time taken to access the average memory

When direct mapping is utilized, 1. when the block has a 16-byte size.

Given that the memory access time (m) is 20ns and the cache access time (Tc) is 10ns, the cache miss rate is 10%, or 0.1(1-H).

AMAT = HTc + (1-H)(Tc+m) Cache hit rate (H) = 0.9

=HTc + Tc + m -HTc - Hm = Tc + (1-H)m = 10 ns + 0.1 x 20 = 10 ns + 2 = 12 ns

2. direct mapped cache with a 32-byte block size.

Given that the access time to the cache and memory is equal to 10 nanoseconds,

Because of the 25% reduction in the question's cache miss rate, the cache miss rate (1-H) is 0.075. The new miss rate is 75% of 0.1, or 0.075.

Tc + (1-H)m' = 10+0.075 x 25 = 10 + 1.875 = 11.875 ns is what AMAT is.

when there is two-set associativity.

1. when a 16-byte block is in use.

The question indicates that the time it takes to access the new cache goes up by 20% of 10ns.

Access time to the new cache, T'c=12ns

The rate of misses went down by 40%, so the new miss rate is 60% of 0.1. which equals 0.006 (1-H').

AMAT = T'c + (1-H')m.

AMAT is equal to 13.2 ns for 12 ns plus 0.06 x 20.

2. when a cache block is 32 bytes in size.

Access time to memory (m') equals 25 nanoseconds.

By increasing the block size, the miss rate is reduced by 25%.

Therefore, the miss rate is 0.045 = (1-H')/75% of 0.06

AMAT is 12 + 0.45 * 25 = 12 + 1.125, or 13.125 ns.

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