You are given the following design parameters, fill in the table: All memory addresses are 32-bit long; A 64Kbyte (2^16 byte) cache is added between the processor and the memory. (64Kbytes do not include the amount of space used to store tags and status bits); There are two associativity choices for the cache: direct-mapped and 2-way set associative. There is a 20 percent increase in cache access time and a 40 percent miss rate reduction when moving from a direct-mapped cache to a 2-way set associative cache: There are two cache block size choices of 16bytes and 32bytes. It takes 20 ns to retrieve 1 Gbytes of data from the main memory and 25 ns to retrieve 32 bytes of data. The cache returns the value to the processor after the entire cache block is filled. However, the cache miss rate is reduced by 25 percent when the cache block size doubles; It takes 10ns to access a 64Kbyte direct-mapped cache; The cache nuss rate for a 64Kbyte direct-mapped cache is 10 percent